Aspects are related generally to integrated circuit design, and more specifically to layout effect characterization for integrated circuits.
As technology structure sizes have been reduced, transistor circuit layout and interconnecting structure have been observed to impact extended circuit behavior and characteristics. For example, signal propagation delays may change depending on layout and structure variations in functionally equivalent circuits. Typical testing systems use a ring oscillator or single transistor characterization analysis to monitor current, timing, and other parameters. Ring oscillators can support frequency changes but typically do not show transition impacts. Ring oscillators also operate at a relatively low frequency at chip output pins for reliable measurements.
Existing test systems can require complicated structures to measure the desired characteristics of interest with accuracy. Layout dependent effects can be so small that they may not be directly measurable at the individual transistor level. Individual transistor measurements may produce generalized results making it difficult to distinguish a weak transistor due to manufacturing process issues, such as doping, versus layout effects.
When asymmetric attributes of individual devices in a chain are observed under certain operating conditions, there can be different rising and falling edge propagation speeds. As chains of devices are arranged in various orientations, the collective effects may vary such that the overall timing of an as-built circuit varies from the as-designed circuit significantly enough to result in fault conditions. In some examples, an oscillating input to a chain of devices, such as inverters, does not fully propagate through the chain due to layout effects.
At present, there is a need for circuits, systems, and methods to perform layout effect characterization for integrated circuits, such that design parameters can be monitored and adjusted at design time and/or after manufacturing.